{"id":194,"date":"2020-07-21T10:08:24","date_gmt":"2020-07-21T14:08:24","guid":{"rendered":"https:\/\/web.uri.edu\/lab-template\/?page_id=194"},"modified":"2026-10-05T21:15:57","modified_gmt":"2026-10-06T01:15:57","slug":"publications","status":"publish","type":"page","link":"https:\/\/web.uri.edu\/comparch\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\"><strong>Resit Sendag<\/strong> is shown in bold and \u2605 marks award-winning papers.<\/p>\n\n<section class=\"cl-wrapper cl-tabs-wrapper\"><div class=\"cl-tabs  \">\n<section class=\"cl-tab \"><h1>2020 \u2013 present<\/h1>\n\n<h3 class=\"wp-block-heading\">2026<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Matthew Constant and <strong>Resit Sendag<\/strong>, \u201c<em>The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction,<\/em>\u201d 38th IEEE\/SBC International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Madrid, Spain, October 2026 (to appear). <mark class=\"has-inline-color\">\u2605 Best Paper Candidate<\/mark> <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/01_SBAC-PAD_2026_Fallacy_of_Independent_Ceilings_Best_Paper_Candidate.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n\n<li>Mehmet Seckin, Yashwant Ponnangati, Ankur Shah, <strong>Resit Sendag<\/strong>, and Kunal Mankodiya, \u201c<em>CysticCare: An Evaluation-Driven RAG AI Chatbot Targeted Towards Evidence-Based Patient Education,<\/em>\u201d IEEE International Conference on AI x Medicine, Health, and Care (AIxMHC), 2026. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/10_IEEE_AIxMHC_2026_CysticCare_RAG_Patient_Education_Chatbot.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n\n<li>Harishjitu Saseendran, Manbir Sodhi, and <strong>Resit Sendag<\/strong>, \u201c<em>LLM-Driven Configuration of Genetic Algorithms for Constraint-Rich Optimization Problems,<\/em>\u201d 16th Workshop on Evolutionary Computation for the Automated Design of Algorithms (ECADA), in conjunction with the ACM Genetic and Evolutionary Computation Conference (GECCO), San Jos\u00e9, Costa Rica, 2026. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/09_ACM_GECCO-ECADA_2026_LLM-Driven_GA_Configuration.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2025<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>A. A. Miah, K. Icer, <strong>Resit Sendag<\/strong>, and Y. Bi, \u201c<em>Noise Attack: An Evasive Sample-Specific Multi-Targeted Backdoor Attack through White Gaussian Noise,<\/em>\u201d International Journal of Information Technology, 2025. (Preprint: arXiv:2409.02251, 2024.) <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/NoiseAttackPaper.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2023<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Maximilian Jakob Heer, Jos\u00e9 Quevedo, Marwan F. Abdelatti, <strong>Resit Sendag<\/strong>, and Manbir Sodhi, \u201c<em>Efficient Implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGA,<\/em>\u201d IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023.<\/li>\n\n\n<li>Jos\u00e9 Quevedo, Maximilian Jakob Heer, Marwan F. Abdelatti, <strong>Resit Sendag<\/strong>, and Manbir Sodhi, \u201c<em>Performance Comparison of Steady State GAs and Generational GAs for Capacitated Vehicle Routing Problems,<\/em>\u201d ACM Conference on Genetic and Evolutionary Computation (GECCO), 2023.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2022<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Marwan Abdelatti, Manbir Sodhi, and <strong>Resit Sendag<\/strong>, \u201c<em>A Multi-GPU Parallel Genetic Algorithm for Large-Scale Vehicle Routing Problems,<\/em>\u201d IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, September 2022.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2021<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Mustafa Cavus, Mohammed Shatnawi, <strong>Resit Sendag<\/strong>, and Augustus Uht, \u201c<em>Fast Key-Value Lookups with Node Tracker,<\/em>\u201d ACM Transactions on Architecture and Code Optimization (TACO), vol. 18, no. 3, pp. 1\u201326, June 2021. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/03_ACM_TACO_2021_Node_Tracker_Fast_Key-Value_Lookups.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2020<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Mustafa Cavus, Mohammed Shatnawi, <strong>Resit Sendag<\/strong>, and Augustus Uht, \u201c<em>Exploring Prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory Database Lookups,<\/em>\u201d IEEE Computer Architecture Letters (CAL), 2020. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/04_IEEE_CAL_2020_Prefetching_PreExecution_Branch_Outcome_Streaming.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n\n<li>Mustafa Cavus, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>Informed Prefetching for Indirect Memory Accesses,<\/em>\u201d ACM Transactions on Architecture and Code Optimization (TACO), vol. 17, no. 1, pp. 1\u201329, March 2020. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/05_ACM_TACO_2020_Informed_Prefetching_Indirect_Memory_Accesses.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n<\/ul>\n\n<\/section>\n<section class=\"cl-tab \"><h1>2010 \u2013 2019<\/h1>\n\n<h3 class=\"wp-block-heading\">2018<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Mustafa Cavus, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>Array Tracking Prefetcher for Indirect Accesses,<\/em>\u201d IEEE International Conference on Computer Design (ICCD), Orlando, FL, October 2018.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2017<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Babak Falsafi, Bill Dally, Desh Singh, Derek Chiou, Joshua J. Yi, and <strong>Resit Sendag<\/strong>, \u201c<em>FPGAs versus GPUs in Data Centers,<\/em>\u201d IEEE Micro, vol. 37, no. 1, pp. 60\u201372, 2017. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/14_IEEE_Micro_2017_FPGAs_vs_GPUs_in_Datacenters_CARD.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2016<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Trevor N. Mudge, Frederic T. Chong, Igor L. Markov, <strong>Resit Sendag<\/strong>, Joshua J. Yi, and Derek Chiou, \u201c<em>Impact of Future Technologies on Architecture,<\/em>\u201d IEEE Micro, vol. 36, no. 4, pp. 48\u201356, 2016.<\/li>\n\n\n<li>Mark D. Hill, Dave Christie, David A. Patterson, Joshua J. Yi, Derek Chiou, and <strong>Resit Sendag<\/strong>, \u201c<em>Proprietary versus Open Instruction Sets,<\/em>\u201d IEEE Micro, vol. 36, no. 4, pp. 58\u201368, 2016. <a href=\"https:\/\/web.uri.edu\/comparch\/wp-content\/uploads\/sites\/1928\/13_IEEE_Micro_2016_Proprietary_vs_Open_Instruction_Sets_CARD.pdf\" target=\"_blank\" rel=\"noopener\">[PDF]<\/a><\/li>\n\n\n<li>Mustafa Cavus and <strong>Resit Sendag<\/strong>, \u201c<em>A Sequential Prefetcher with Adaptive Distance,<\/em>\u201d Annual Boston Area Computer Architecture Workshop (BARC), Boston, MA, 2016.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2015<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Mustafa Cavus, Ibrahim Karsli, and <strong>Resit Sendag<\/strong>, \u201c<em>Prefetching On-time and When it Works,<\/em>\u201d 2nd Data Prefetching Championship (DPC-2), in conjunction with ISCA-42, Portland, OR, June 2015. <mark class=\"has-inline-color\">\u2605 3rd Place<\/mark><\/li>\n\n\n<li>Nathan Brown and <strong>Resit Sendag<\/strong>, \u201c<em>Sandbox Based Optimal Offset Estimation,<\/em>\u201d 2nd Data Prefetching Championship (DPC-2), in conjunction with ISCA-42, Portland, OR, June 2015.<\/li>\n\n\n<li>Ibrahim Burak Karsli and <strong>Resit Sendag<\/strong>, \u201c<em>Quantifying Memory Address Patterns with PatternFinder,<\/em>\u201d Annual Boston Area Computer Architecture Workshop (BARC), Boston, MA, 2015.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2014<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Celal Ozturk, Ibrahim Karsli, and <strong>Resit Sendag<\/strong>, \u201c<em>An Analysis of Address and Branch Patterns with PatternFinder,<\/em>\u201d IEEE International Symposium on Workload Characterization (IISWC), Raleigh, NC, October 2014.<\/li>\n\n\n<li>Celal Ozturk and <strong>Resit Sendag<\/strong>, \u201c<em>Automatic Source Code Analysis of Branch Mispredictions,<\/em>\u201d IEEE International Symposium on Workload Characterization (IISWC), Raleigh, NC, October 2014.<\/li>\n\n\n<li>Ibrahim Karsli and <strong>Resit Sendag<\/strong>, \u201c<em>T-BAG: Bootstrap Aggregating the TAGE Predictor,<\/em>\u201d 4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), in conjunction with ISCA-41, Minneapolis, MN, June 2014. <mark class=\"has-inline-color\">\u2605 4th Place<\/mark><\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2013<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Ronald Duarte, <strong>Resit Sendag<\/strong>, and Fred Vetter, \u201c<em>On the Performance and Energy-Efficiency of Multi-core SIMD CPUs and CUDA-enabled GPUs,<\/em>\u201d IEEE International Symposium on Workload Characterization (IISWC), Portland, OR, September 2013.<\/li>\n\n\n<li>Andre Zierfuss and <strong>Resit Sendag<\/strong>, \u201c<em>The Impact of Data Complexity on Privacy Management in Vehicle-to-Infrastructure Applications,<\/em>\u201d IEEE International Conference on Connected Vehicles and Expo (ICCVE), Las Vegas, NV, pp. 753\u2013760, 2013.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2012<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Ronald Duarte and <strong>Resit Sendag<\/strong>, \u201c<em>Accelerating and Characterizing Seam Carving Using a Heterogeneous CPU-GPU System,<\/em>\u201d International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), July 2012.<\/li>\n\n\n<li>Will Simoneau and <strong>Resit Sendag<\/strong>, \u201c<em>An FPGA-based Multi-Core Platform for Testing and Analysis of Architectural Techniques,<\/em>\u201d IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), New Brunswick, NJ, April 2012.<\/li>\n\n\n<li>Ronald Duarte and <strong>Resit Sendag<\/strong>, \u201c<em>Real-time Video and Image Resizing using CUDA-Enabled GPUs,<\/em>\u201d 3rd Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-3), in conjunction with HPCA-18, New Orleans, LA, February 2012.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2011<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Peng-fei Chuang, Celal Ozturk, Khun Ban, Huijun Yan, Kingsum Chow, and <strong>Resit Sendag<\/strong>, \u201c<em>Impact of Java Application Server Evolution on Computer System Performance,<\/em>\u201d Workshop on Modeling, Benchmarking and Simulation (MoBS), in conjunction with ISCA, June 2011.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2010<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>James C. Hoe, Doug Burger, Joel Emer, Derek Chiou, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>The Future of Architectural Simulation,<\/em>\u201d IEEE Micro, pp. 8\u201318, May\/June 2010.<\/li>\n\n\n<li>Arvind, David August, Keshav Pingali, Derek Chiou, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?,<\/em>\u201d IEEE Micro, pp. 19\u201333, May\/June 2010.<\/li>\n\n\n<li>Celal Ozturk and <strong>Resit Sendag<\/strong>, \u201c<em>An Analysis of Hard to Predict Branches,<\/em>\u201d IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), White Plains, NY, March 2010.<\/li>\n\n<\/ul>\n\n<\/section>\n<section class=\"cl-tab \"><h1>2000 \u2013 2009<\/h1>\n\n<h3 class=\"wp-block-heading\">2009<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Sharookh Daruwalla, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>Adaptive Simulation Sampling Using an Autoregressive Framework,<\/em>\u201d IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos, Greece, July 2009.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2008<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Resit Sendag<\/strong>, Joshua J. Yi, Peng-fei Chuang, and David J. Lilja, \u201c<em>Low Power\/Area Branch Prediction Using Complementary Branch Predictors,<\/em>\u201d IEEE International Parallel and Distributed Processing Symposium (IPDPS), April 2008.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2007<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Resit Sendag<\/strong>, Ayse Yilmazer, Joshua J. Yi, and Augustus K. Uht, \u201c<em>The Impact of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems,<\/em>\u201d Journal of Parallel and Distributed Computing (JPDC), Special Issue on Best Papers of IPDPS, vol. 67, no. 12, pp. 1256\u20131269, December 2007.<\/li>\n\n\n<li>Antonio Gonz\u00e1lez, Scott Mahlke, Shubu Mukherjee, <strong>Resit Sendag<\/strong>, Derek Chiou, and Joshua J. Yi, \u201c<em>Reliability: Fallacy or Reality?,<\/em>\u201d IEEE Micro, vol. 27, no. 6, pp. 36\u201345, November\/December 2007.<\/li>\n\n\n<li>Kevin Skadron, Pradip Bose, Kanad Ghose, <strong>Resit Sendag<\/strong>, Joshua J. Yi, and Derek Chiou, \u201c<em>Low-Power Design and Temperature Management,<\/em>\u201d IEEE Micro, vol. 27, no. 6, pp. 46\u201357, November\/December 2007.<\/li>\n\n\n<li>Joel Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, and <strong>Resit Sendag<\/strong>, \u201c<em>Single-Threaded vs. Multithreaded: Where Should We Focus?,<\/em>\u201d IEEE Micro, vol. 27, no. 6, pp. 14\u201324, November\/December 2007.<\/li>\n\n\n<li>Shay Gueron, Jean-Pierre Seifert, Geoffrey Strongin, Derek Chiou, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>Where Does Security Stand? New Vulnerabilities vs. Trusted Computing,<\/em>\u201d IEEE Micro, vol. 27, no. 6, pp. 25\u201335, November\/December 2007.<\/li>\n\n\n<li>Joshua J. Yi, <strong>Resit Sendag<\/strong>, David J. Lilja, and Douglas M. Hawkins, \u201c<em>Speed versus Accuracy Trade-Offs in Microarchitectural Simulations,<\/em>\u201d IEEE Transactions on Computers, vol. 56, no. 11, pp. 1549\u20131563, November 2007.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Joshua J. Yi, and Peng-fei Chuang, \u201c<em>Branch Misprediction Prediction: Complementary Branch Predictors,<\/em>\u201d IEEE Computer Architecture Letters (CAL), September 2007.<\/li>\n\n\n<li>Ayse Yilmazer, <strong>Resit Sendag<\/strong>, and Joshua J. Yi, \u201c<em>Quantifying and Comparing the Impact of Wrong-Path Memory References in Multiple-CMP Systems,<\/em>\u201d Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), in conjunction with HPCA-13, February 2007.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Joshua J. Yi, and Peng-fei Chuang, \u201c<em>Predicting When a Branch Predictor Will Fail,<\/em>\u201d Boston Area Computer Architecture Workshop (BARC), January 2007.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2006<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Joshua J. Yi, <strong>Resit Sendag<\/strong>, Lieven Eeckhout, Ajay Joshi, David J. Lilja, and Lizy K. John, \u201c<em>Evaluating Benchmark Subsetting Approaches,<\/em>\u201d IEEE International Symposium on Workload Characterization (IISWC), October 2006.<\/li>\n\n\n<li>Emre Ozer, <strong>Resit Sendag<\/strong>, and David Gregg, \u201c<em>Multiple-Valued Logic Buses for Reducing Bus Energy in Low-Power Systems,<\/em>\u201d IEE Proceedings \u2013 Computers and Digital Techniques, vol. 153, no. 4, pp. 270\u2013282, July 2006.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Ayse Yilmazer, Joshua J. Yi, and Augustus K. Uht, \u201c<em>Quantifying and Reducing the Effects of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems,<\/em>\u201d IEEE International Parallel and Distributed Processing Symposium (IPDPS), April 2006. <mark class=\"has-inline-color\">\u2605 Best Paper Award<\/mark><\/li>\n\n\n<li>Ayse Yilmazer, <strong>Resit Sendag<\/strong>, Joshua J. Yi, and Augustus K. Uht, \u201c<em>Investigating the Effects of Wrong-Path Memory References in Shared-Memory Multiprocessor Systems,<\/em>\u201d Boston Area Computer Architecture Workshop (BARC), February 2006.<\/li>\n\n\n<li>Joshua J. Yi, Ajay Joshi, <strong>Resit Sendag<\/strong>, Lieven Eeckhout, and David J. Lilja, \u201c<em>Analyzing the Processor Bottlenecks in SPEC CPU 2000,<\/em>\u201d SPEC Benchmark Workshop, January 2006. <mark class=\"has-inline-color\">\u2605 Best Paper Award (Kaivalya Dixit Award)<\/mark><\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2005<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Joshua J. Yi, <strong>Resit Sendag<\/strong>, and David J. Lilja, \u201c<em>Instruction Precomputation: Dynamically Removing Redundant Computations Using Profiling,<\/em>\u201d Chapter 10 in Speculative Execution in Modern Computer Architectures, P.-C. Yew and D. Kaeli (Eds.), CRC Press, 2005. ISBN 1-58488-447-9.<\/li>\n\n\n<li>Emre Ozer, <strong>Resit Sendag<\/strong>, and David Gregg, \u201c<em>Multiple-Valued Logic Buses for Reducing Bus Size, Transitions and Power in Deep Submicron Technologies,<\/em>\u201d Advanced Networking and Communications Hardware Workshop (ANCHOR), in conjunction with ISCA-32, June 2005.<\/li>\n\n\n<li>Emre Ozer, <strong>Resit Sendag<\/strong>, and David Gregg, \u201c<em>Multiple-Valued Caches for Power-Efficient Embedded Systems,<\/em>\u201d IEEE International Symposium on Multiple-Valued Logic (ISMVL-35), Calgary, Canada, May 2005.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Ying Chen, and David J. Lilja, \u201c<em>The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture,<\/em>\u201d IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 16, no. 3, pp. 271\u2013285, March 2005.<\/li>\n\n\n<li>Joshua J. Yi, Sreekumar Kodakara, <strong>Resit Sendag<\/strong>, David J. Lilja, and Douglas M. Hawkins, \u201c<em>Characterizing and Comparing Prevailing Simulation Techniques,<\/em>\u201d IEEE International Symposium on High-Performance Computer Architecture (HPCA-11), pp. 266\u2013277, February 2005.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2004<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li>Peng-fei Chuang, <strong>Resit Sendag<\/strong>, and David J. Lilja, \u201c<em>Improving Data Cache Performance via Address Correlation: An Upper Bound Study,<\/em>\u201d Euro-Par 2004, Lecture Notes in Computer Science, vol. 3149, pp. 541\u2013550, September 2004.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Peng-fei Chuang, and David J. Lilja, \u201c<em>Address Correlation,<\/em>\u201d Boston Area Computer Architecture Workshop (BARC), January 2004.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2003<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Resit Sendag<\/strong>, Peng-fei Chuang, and David J. Lilja, \u201c<em>Address Correlation: Exceeding the Limits of Locality,<\/em>\u201d IEEE Computer Architecture Letters (CAL), vol. 2, May 2003.<\/li>\n\n\n<li>Ying Chen, <strong>Resit Sendag<\/strong>, and David J. Lilja, \u201c<em>Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor,<\/em>\u201d IEEE International Parallel and Distributed Processing Symposium (IPDPS), April 2003.<\/li>\n\n\n<li>Keqiang Wu, <strong>Resit Sendag<\/strong>, and David J. Lilja, \u201c<em>Exploring the Memory Access Regularity in Pointer-Intensive Application Programs,<\/em>\u201d 4th International Conference on Intelligent Data Engineering and Automated Learning (IDEAL), Lecture Notes in Computer Science, vol. 2690, pp. 472\u2013476, March 2003.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2002<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Resit Sendag<\/strong>, Ying Chen, and David J. Lilja, \u201c<em>The Effect of Executing Mispredicted Load Instructions on Speculative Multithreaded Architecture,<\/em>\u201d 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), in conjunction with IEEE MICRO-35, pp. 19\u201326, November 2002.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, David J. Lilja, and Steven R. Kunkel, \u201c<em>Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions,<\/em>\u201d Euro-Par 2002, Lecture Notes in Computer Science, vol. 2400, pp. 468\u2013480, 2002.<\/li>\n\n\n<li>Joshua J. Yi, <strong>Resit Sendag<\/strong>, and David J. Lilja, \u201c<em>Increasing Instruction-Level Parallelism with Instruction Precomputation,<\/em>\u201d Euro-Par 2002, Lecture Notes in Computer Science, vol. 2400, pp. 481\u2013485, 2002.<\/li>\n\n<\/ul>\n\n\n<h3 class=\"wp-block-heading\">2001<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Resit Sendag<\/strong> and A. Hamit Serbest, \u201c<em>Scattering at the Junction Formed by a PEC Half-Plane and a Half-Plane with Anisotropic Conductivity,<\/em>\u201d Electromagnetics, vol. 21, no. 5, pp. 415\u2013435, 2001.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Peng-fei Chuang, and David H. C. Du, \u201c<em>Routing and Wavelength Assignment in Optical Passive Star Networks with Non-uniform Traffic Load,<\/em>\u201d IEEE GLOBECOM \u201901, vol. 3, pp. 1435\u20131439, 2001.<\/li>\n\n<\/ul>\n\n<\/section>\n<section class=\"cl-tab \"><h1>Earlier<\/h1>\n\n<h3 class=\"wp-block-heading\">1998<\/h3>\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Resit Sendag<\/strong> and A. Hamit Serbest, \u201c<em>Scattering of Plane Electromagnetic Waves at the Junction Formed by a PEC Half-Plane and a Half-Plane with Anisotropic Conductivity,<\/em>\u201d 9th IEEE Mediterranean Electrotechnical Conference (MELECON \u201998), vol. 1, pp. 278\u2013282, 1998.<\/li>\n\n\n<li><strong>Resit Sendag<\/strong>, Michael A. Lyalinov, and A. Hamit Serbest, \u201c<em>Perturbation Method in the Problem of Diffraction of an Obliquely Incident Plane Wave by a Wedge with Different Surface Impedances,<\/em>\u201d URSI \u201998 Electromagnetic Theory Symposium, Thessaloniki, Greece, May 1998.<\/li>\n\n<\/ul>\n\n<\/section>\n<section class=\"cl-tab \"><h1>Patents<\/h1>\n\n<ul class=\"wp-block-list\">\n<li>Reza Abiri, Ali Rabiee, Resit Sendag, and Mohammad Hassan Farhadi, \u201cDeliberate Interactive Cobot for Autonomy Allocation and Human-Robot Teaming,\u201d US Patent Application, filed May 2026.<\/li>\n\n\n<li>Resit Sendag, \u201cBranch Prediction Enhancement Method and Mechanism,\u201d US Patent No. 8,312,255, issued 2012.<\/li>\n\n\n<li>Resit Sendag, Ayse Yilmazer, and Augustus K. Uht, \u201cWrong-Path Aware Replacement Policy in Cache-Coherent Shared Memory Multiprocessor Systems,\u201d US Patent No. 7,721,048, issued May 2010.<\/li>\n\n<\/ul>\n\n<\/section>\n<\/div><\/section>\n","protected":false},"excerpt":{"rendered":"<p>Resit Sendag is shown in bold and \u2605 marks award-winning papers.<\/p>\n","protected":false},"author":0,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":"","_links_to":"","_links_to_target":""},"class_list":["post-194","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages\/194","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/types\/page"}],"replies":[{"embeddable":true,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/comments?post=194"}],"version-history":[{"count":5,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages\/194\/revisions"}],"predecessor-version":[{"id":718,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages\/194\/revisions\/718"}],"wp:attachment":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/media?parent=194"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}