{"id":397,"date":"2020-09-16T15:47:48","date_gmt":"2020-09-16T19:47:48","guid":{"rendered":"https:\/\/web.uri.edu\/comparch\/?page_id=397"},"modified":"2026-10-05T21:10:54","modified_gmt":"2026-10-06T01:10:54","slug":"projects","status":"publish","type":"page","link":"https:\/\/web.uri.edu\/comparch\/projects\/","title":{"rendered":"Research & Projects"},"content":{"rendered":"\n

Our research spans the computing stack from microarchitecture to systems software. We build simulators, analysis tools and FPGA prototypes to understand where performance and energy go \u2014 and invent hardware and software mechanisms to recover them.<\/p>\n\n

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Microarchitecture<\/h1>\n\n

Branch Prediction & Speculative Execution<\/h3>\n\n\n

Complementary branch predictors that anticipate when the main predictor will fail; bootstrap-aggregated TAGE predictors (4th place, CBP-4); analysis of hard-to-predict branches and automatic source-code analysis of mispredictions; and the impact of wrong-path memory references in multithreaded and cache-coherent multiprocessor systems (IEEE IPDPS Best Paper Award).<\/p>\n\n\n

Current work characterizes how load and branch stalls interact in out-of-order cores (SBAC-PAD 2026 Best Paper Candidate) and explores execution-stage overprovisioning and programmable logic integrated into CPU cores.<\/p>\n\n<\/section>\n

Memory Systems<\/h1>\n\n

Memory Hierarchy & Prefetching<\/h3>\n\n\n

Address correlation; sequential and offset prefetchers (3rd place, Intel DPC-2); informed and array-tracking prefetchers for indirect memory accesses (ACM TACO, ICCD); prefetching, pre-execution and branch-outcome streaming for in-memory key-value and database lookups; and multi-layer prefetcher interaction.<\/p>\n\n<\/section>\n

Patterns & Workloads<\/h1>\n\n

Pattern-Aware Design<\/h3>\n\n\n

An NSF-funded effort to quantify dynamic program behavior through recurring patterns and regularities in address and branch streams, and to use them to guide hardware design.<\/p>\n\n\n

Simulation Methodology & Workload Characterization<\/h3>\n\n\n

Statistically rigorous simulation, speed-versus-accuracy trade-offs, benchmark subsetting, processor-bottleneck analysis of SPEC CPU (SPEC Kaivalya Dixit Best Paper Award), and characterization of Java server and data-parallel workloads.<\/p>\n\n<\/section>\n

Accelerators<\/h1>\n\n

Heterogeneous & Reconfigurable Computing<\/h3>\n\n\n

FPGA-based multicore platforms; CPU\u2013GPU heterogeneous systems and energy efficiency of SIMD CPUs versus GPUs; FPGA and multi-GPU parallel genetic algorithms for large-scale vehicle-routing and mission-planning problems (Office of Naval Research); and hardware accelerators for large language models.<\/p>\n\n<\/section>\n

AI & Security<\/h1>\n\n

AI Hardware, Security & Generative AI<\/h3>\n\n\n

Energy-efficient AI agent systems; backdoor attacks on deep neural networks; LLM-driven configuration of optimization algorithms; AI agents for hardware design; retrieval-augmented chatbots for patient education; and assistive human-robot teaming.<\/p>\n\n<\/section>\n<\/div><\/section>\n\n

Projects & Tools<\/h2>\n\n\n
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PatternFinder<\/h2>

A generalized pattern-analysis tool for quantitatively analyzing program behavior in terms of regularities and patterns in large execution traces. Developed with Celal Ozturk and Peter Morley; funded in part by NSF Award 1422516.<\/p><\/div><\/div>

PatternFinder website<\/div><\/a><\/div>\n<\/div>\n\n\n
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z4800 Multicore Platform on FPGA<\/h2>

An open-source synthesizable soft-core CPU with supporting hardware and software. Reference designs build a complete FPGA computer running a full-featured operating system, with an extendable performance-counter system for benchmark studies.<\/p><\/div><\/div>

z4800 documentation<\/div><\/a><\/div>\n<\/div>\n\n<\/div>\n\n\n
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CARD Workshop<\/h2>

Computer Architecture Research Directions panels (2007\u20132019) featuring leading architects debating the field’s big questions. Recordings have been downloaded more than 80,000 times, and two IEEE Micro special issues featured the workshop.<\/p><\/div><\/div>

CARD recordings<\/div><\/a><\/div>\n<\/div>\n\n\n
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\"URI<\/div>

Generative AI Development Team<\/h2>

AI-agent applications for URI, including the ECBE Graduate Program Chatbot and an undergraduate advising chatbot with transcript-based degree audits and course suggestions.<\/p><\/div><\/div>

Try the chatbot<\/div><\/a><\/div>\n<\/div>\n\n<\/div>\n\n\n

Patents<\/h2>\n\n\n
    \n
  • Reza Abiri, Ali Rabiee, Resit Sendag, and Mohammad Hassan Farhadi, \u201cDeliberate Interactive Cobot for Autonomy Allocation and Human-Robot Teaming,\u201d US Patent Application, filed May 2026.<\/li>\n\n\n
  • Resit Sendag, \u201cBranch Prediction Enhancement Method and Mechanism,\u201d US Patent No. 8,312,255, issued 2012.<\/li>\n\n\n
  • Resit Sendag, Ayse Yilmazer, and Augustus K. Uht, \u201cWrong-Path Aware Replacement Policy in Cache-Coherent Shared Memory Multiprocessor Systems,\u201d US Patent No. 7,721,048, issued May 2010.<\/li>\n\n<\/ul>\n\n\n

    Sponsors<\/h2>\n\n\n

    The lab\u2019s research has been supported by funding from the National Science Foundation, the Office of Naval Research, Freescale Semiconductor and the Champlin Foundation.<\/p>\n\n","protected":false},"excerpt":{"rendered":"

    Our research spans the computing stack from microarchitecture to systems software. We build simulators, analysis tools and FPGA prototypes to understand where performance and energy go \u2014 and invent hardware and software mechanisms to recover them. Projects & Tools Patents Sponsors The lab\u2019s research has been supported by funding from the National Science Foundation, the […]<\/p>\n","protected":false},"author":3931,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":"","_links_to":"","_links_to_target":""},"class_list":["post-397","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages\/397","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/users\/3931"}],"replies":[{"embeddable":true,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/comments?post=397"}],"version-history":[{"count":5,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages\/397\/revisions"}],"predecessor-version":[{"id":716,"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/pages\/397\/revisions\/716"}],"wp:attachment":[{"href":"https:\/\/web.uri.edu\/comparch\/wp-json\/wp\/v2\/media?parent=397"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}