Jien-Chung Lo

  • Professor
  • Electrical, Computer and Biomedical Engineering
  • Phone: 401.874.2996
  • Email: jclce@uri.edu
  • Office Location: Fascitelli Center for Advanced Engineering, Rm 406
  • Website


  • Digital Circuit Designs on FPGA
  • VLSI Testing and Reliability
  • System-on-Chip and Hardware Accelerators


  • Ph.D., Computer Engineering, University of Southwester Louisiana, 1989
  • M.S., Computer Engineering, University of Southwestern Louisiana, 1987
  • B.S., Electronics Engineering, Taipei University of Technology, 1981


  • Lo J-C, Chuen-Song C, Inventors; Rhode Island Board of Education, Assignee. Systems and Methods for On-Chip Power Management. US Patent 7902802. March 8, 2011
  • Jenkins KA, Lo J-C, Song P, Xia T, Inventors; LinkedIn Corp., Assignee. Programmable Jitter Signal Generator. US Patent August 22, 2006
  • Williams EL, Martin HL, Lo J-C, Inventors; US Secretary of Navy, Assignee. Check Bit Code Circuit for Simultaneous Single Bit Error Correction and Burst Error Detection. US Patent October 10, 1995

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