Our research spans the computing stack from microarchitecture to systems software. We build simulators, analysis tools and FPGA prototypes to understand where performance and energy go — and invent hardware and software mechanisms to recover them.
Microarchitecture
Branch Prediction & Speculative Execution
Complementary branch predictors that anticipate when the main predictor will fail; bootstrap-aggregated TAGE predictors (4th place, CBP-4); analysis of hard-to-predict branches and automatic source-code analysis of mispredictions; and the impact of wrong-path memory references in multithreaded and cache-coherent multiprocessor systems (IEEE IPDPS Best Paper Award).
Current work characterizes how load and branch stalls interact in out-of-order cores (SBAC-PAD 2026 Best Paper Candidate) and explores execution-stage overprovisioning and programmable logic integrated into CPU cores.
Memory Systems
Memory Hierarchy & Prefetching
Address correlation; sequential and offset prefetchers (3rd place, Intel DPC-2); informed and array-tracking prefetchers for indirect memory accesses (ACM TACO, ICCD); prefetching, pre-execution and branch-outcome streaming for in-memory key-value and database lookups; and multi-layer prefetcher interaction.
Patterns & Workloads
Pattern-Aware Design
An NSF-funded effort to quantify dynamic program behavior through recurring patterns and regularities in address and branch streams, and to use them to guide hardware design.
Simulation Methodology & Workload Characterization
Statistically rigorous simulation, speed-versus-accuracy trade-offs, benchmark subsetting, processor-bottleneck analysis of SPEC CPU (SPEC Kaivalya Dixit Best Paper Award), and characterization of Java server and data-parallel workloads.
Accelerators
Heterogeneous & Reconfigurable Computing
FPGA-based multicore platforms; CPU–GPU heterogeneous systems and energy efficiency of SIMD CPUs versus GPUs; FPGA and multi-GPU parallel genetic algorithms for large-scale vehicle-routing and mission-planning problems (Office of Naval Research); and hardware accelerators for large language models.
AI & Security
AI Hardware, Security & Generative AI
Energy-efficient AI agent systems; backdoor attacks on deep neural networks; LLM-driven configuration of optimization algorithms; AI agents for hardware design; retrieval-augmented chatbots for patient education; and assistive human-robot teaming.
Projects & Tools
Patents
- Reza Abiri, Ali Rabiee, Resit Sendag, and Mohammad Hassan Farhadi, “Deliberate Interactive Cobot for Autonomy Allocation and Human-Robot Teaming,” US Patent Application, filed May 2026.
- Resit Sendag, “Branch Prediction Enhancement Method and Mechanism,” US Patent No. 8,312,255, issued 2012.
- Resit Sendag, Ayse Yilmazer, and Augustus K. Uht, “Wrong-Path Aware Replacement Policy in Cache-Coherent Shared Memory Multiprocessor Systems,” US Patent No. 7,721,048, issued May 2010.
Sponsors
The lab’s research has been supported by funding from the National Science Foundation, the Office of Naval Research, Freescale Semiconductor and the Champlin Foundation.